Ошибка 4013 при восстановлении iphone
Содержание:
Параметры
| Parameters / Models | 89267AKB3T | CD4013BE | CD4013BEE4 | CD4013BF3AS2534 | CD4013BM | CD4013BM96 | CD4013BM96E4 | CD4013BM96G4 | CD4013BME4 | CD4013BMG4 | CD4013BMT | CD4013BNSR | CD4013BNSRG4 | CD4013BPW | CD4013BPWR | CD4013BPWRE4 | CD4013BPWRG4 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 3-State Output | No | No | No | No | No | No | No | No | No | No | No | No | No | No | No | No | No |
| Approx. Price (US$) | 0.11 | 1ku | 0.11 | 1ku | |||||||||||||||
| Bits | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | ||
| Bits(#) | 2 | 2 | |||||||||||||||
| F @ Nom Voltage(Max), Mhz | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | ||
| F @ Nom Voltage(Max)(Mhz) | 8 | 8 | |||||||||||||||
| ICC @ Nom Voltage(Max), мА | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | 0.06 | ||
| ICC @ Nom Voltage(Max)(mA) | 0.06 | 0.06 | |||||||||||||||
| Тип входа | CMOS | CMOS | |||||||||||||||
| Рабочий диапазон температур, C | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | от -55 до 125 | ||
| Operating Temperature Range(C) | -55 to 125 | -55 to 125 | |||||||||||||||
| Output Drive (IOL/IOH)(Max), мА | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | 1.5/-1.5 | ||
| Output Drive (IOL/IOH)(Max)(mA) | 1.5/-1.5 | 1.5/-1.5 | |||||||||||||||
| Тип выхода | CMOS | CMOS | |||||||||||||||
| Package Group | PDIPSOSOICTSSOP | PDIP | PDIP | PDIPSOSOICTSSOP | SOIC | SOIC | SOIC | SOIC | SOIC | SOIC | SOIC | SO | SO | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | See datasheet (PDIP) | See datasheet (PDIP) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SO: 80 mm2: 7.8 x 10.2(SO) | 14SO: 80 mm2: 7.8 x 10.2(SO) | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) | ||
| Package Size: mm2:W x L (PKG) | See datasheet (PDIP)See datasheet (CDIP) | See datasheet (PDIP)See datasheet (CDIP) | |||||||||||||||
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No | No | No | No | No | No | No | No | No | No | No | No | No | No | No |
| Technology Family | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 | CD4000 |
| VCC(Max), В | 18 | 18 | 18 | 18 | 18 | 18 | 18 | 18 | 18 | 18 | 18 | 18 | 18 | 18 | 18 | ||
| VCC(Max)(V) | 18 | 18 | |||||||||||||||
| VCC(Min), В | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | ||
| VCC(Min)(V) | 3 | 3 | |||||||||||||||
| Voltage(Nom), В | 10 | 10 | 10 | 10 | 10 | 10 | 10 | 10 | 10 | 10 | 10 | 10 | 10 | 10 | 10 | ||
| Voltage(Nom)(V) | 10 | 10 | |||||||||||||||
| tpd @ Nom Voltage(Max), нс | 130 | 130 | 130 | 130 | 130 | 130 | 130 | 130 | 130 | 130 | 130 | 130 | 130 | 130 | 130 | ||
| tpd @ Nom Voltage(Max)(ns) | 130 | 130 |
Datasheets
Sample &Buy ProductFolder Support &Community Tools &Software TechnicalDocuments CD4013BSCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016 CD4013B CMOS Dual D-Type Flip-Flop1 Features 3 Description The CD4013B device consists of two identical,independent data-type flip-flops. Each flip-flop hasindependent data, set, reset, and clock inputs and Qand Q outputs. These devices can be used for shiftregister applications, and, by connecting Q output tothe data input, for counter and toggle applications.The logic level present at the D input is transferred tothe Q output during the positive-going transition of theclock pulse. Setting or resetting is independent of theclock and is accomplished by a high level on the setor reset line, respectively. 1 Asynchronous Set-Reset CapabilityStatic Flip-Flop OperationMedium-Speed Operation: 16 MHz (Typical) ClockToggle Rate at 10-V SupplyStandardized Symmetrical Output CharacteristicsMaximum Input Current Of 1-ВµA at 18 V Over Full …
Datasheets
Sample &Buy ProductFolder Support &Community Tools &Software TechnicalDocuments CD4013BSCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016 CD4013B CMOS Dual D-Type Flip-Flop1 Features 3 Description The CD4013B device consists of two identical,independent data-type flip-flops. Each flip-flop hasindependent data, set, reset, and clock inputs and Qand Q outputs. These devices can be used for shiftregister applications, and, by connecting Q output tothe data input, for counter and toggle applications.The logic level present at the D input is transferred tothe Q output during the positive-going transition of theclock pulse. Setting or resetting is independent of theclock and is accomplished by a high level on the setor reset line, respectively. 1 Asynchronous Set-Reset CapabilityStatic Flip-Flop OperationMedium-Speed Operation: 16 MHz (Typical) ClockToggle Rate at 10-V SupplyStandardized Symmetrical Output CharacteristicsMaximum Input Current Of 1-ВµA at 18 V Over Full …
Статус
| 89267AKB3T | CD4013BE | CD4013BEE4 | CD4013BF3AS2534 | CD4013BM | CD4013BM96 | CD4013BM96E4 | CD4013BM96G4 | CD4013BME4 | CD4013BMG4 | CD4013BMT | CD4013BNSR | CD4013BNSRG4 | CD4013BPW | CD4013BPWR | CD4013BPWRE4 | CD4013BPWRG4 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Статус продукта | Снят с производства | В производстве | В производстве | Снят с производства | В производстве | В производстве | В производстве | В производстве | В производстве | В производстве | В производстве | В производстве | В производстве | В производстве | В производстве | В производстве | В производстве |
| Доступность образцов у производителя | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет | Нет |
Корпус / Упаковка / Маркировка
| 89267AKB3T | CD4013BE | CD4013BEE4 | CD4013BF3AS2534 | CD4013BM | CD4013BM96 | CD4013BM96E4 | CD4013BM96G4 | CD4013BME4 | CD4013BMG4 | CD4013BMT | CD4013BNSR | CD4013BNSRG4 | CD4013BPW | CD4013BPWR | CD4013BPWRE4 | CD4013BPWRG4 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Pin | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 | 14 |
| Package Type | WR | N | N | J | D | D | D | D | D | D | D | NS | NS | PW | PW | PW | PW |
| Industry STD Term | PDIP | PDIP | CDIP | SOIC | SOIC | SOIC | SOIC | SOIC | SOIC | SOIC | SOP | SOP | TSSOP | TSSOP | TSSOP | TSSOP | |
| JEDEC Code | R-PDIP-T | R-PDIP-T | R-GDIP-T | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | |
| Package QTY | 25 | 25 | 50 | 2500 | 2500 | 2500 | 50 | 50 | 250 | 2000 | 2000 | 90 | 2000 | 2000 | 2000 | ||
| Carrier | TUBE | TUBE | TUBE | LARGE T&R | LARGE T&R | LARGE T&R | TUBE | TUBE | SMALL T&R | LARGE T&R | LARGE T&R | TUBE | LARGE T&R | LARGE T&R | LARGE T&R | ||
| Маркировка | CD4013BE | CD4013BE | CD4013BM | CD4013BM | CD4013BM | CD4013BM | CD4013BM | CD4013BM | CD4013BM | CD4013B | CD4013B | CM013B | CM013B | CM013B | CM013B | ||
| Width (мм) | 6.35 | 6.35 | 6.67 | 3.91 | 3.91 | 3.91 | 3.91 | 3.91 | 3.91 | 3.91 | 5.3 | 5.3 | 4.4 | 4.4 | 4.4 | 4.4 | |
| Length (мм) | 19.3 | 19.3 | 19.56 | 8.65 | 8.65 | 8.65 | 8.65 | 8.65 | 8.65 | 8.65 | 10.3 | 10.3 | 5 | 5 | 5 | 5 | |
| Thickness (мм) | 3.9 | 3.9 | 4.57 | 1.58 | 1.58 | 1.58 | 1.58 | 1.58 | 1.58 | 1.58 | 1.95 | 1.95 | 1 | 1 | 1 | 1 | |
| Pitch (мм) | 2.54 | 2.54 | 2.54 | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 | .65 | .65 | .65 | .65 | |
| Max Height (мм) | 5.08 | 5.08 | 5.08 | 1.75 | 1.75 | 1.75 | 1.75 | 1.75 | 1.75 | 1.75 | 2 | 2 | 1.2 | 1.2 | 1.2 | 1.2 | |
| Mechanical Data |
Datasheets
Sample &Buy ProductFolder Support &Community Tools &Software TechnicalDocuments CD4013BSCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016 CD4013B CMOS Dual D-Type Flip-Flop1 Features 3 Description The CD4013B device consists of two identical,independent data-type flip-flops. Each flip-flop hasindependent data, set, reset, and clock inputs and Qand Q outputs. These devices can be used for shiftregister applications, and, by connecting Q output tothe data input, for counter and toggle applications.The logic level present at the D input is transferred tothe Q output during the positive-going transition of theclock pulse. Setting or resetting is independent of theclock and is accomplished by a high level on the setor reset line, respectively. 1 Asynchronous Set-Reset CapabilityStatic Flip-Flop OperationMedium-Speed Operation: 16 MHz (Typical) ClockToggle Rate at 10-V SupplyStandardized Symmetrical Output CharacteristicsMaximum Input Current Of 1-ВµA at 18 V Over Full …
Application Notes
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Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
PDF, 188 Кб, Файл опубликован: 3 дек 2001Both buffered and unbuffered CMOS B-series gates inverters and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products with applications literature focusing on the attributes and use of the buffered types. This practice has left an imb
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Power-Up Behavior of Clocked Devices (Rev. A)
PDF, 34 Кб, Версия: A, Файл опубликован: 6 фев 2015
Datasheets
Sample &Buy ProductFolder Support &Community Tools &Software TechnicalDocuments CD4013BSCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016 CD4013B CMOS Dual D-Type Flip-Flop1 Features 3 Description The CD4013B device consists of two identical,independent data-type flip-flops. Each flip-flop hasindependent data, set, reset, and clock inputs and Qand Q outputs. These devices can be used for shiftregister applications, and, by connecting Q output tothe data input, for counter and toggle applications.The logic level present at the D input is transferred tothe Q output during the positive-going transition of theclock pulse. Setting or resetting is independent of theclock and is accomplished by a high level on the setor reset line, respectively. 1 Asynchronous Set-Reset CapabilityStatic Flip-Flop OperationMedium-Speed Operation: 16 MHz (Typical) ClockToggle Rate at 10-V SupplyStandardized Symmetrical Output CharacteristicsMaximum Input Current Of 1-ВµA at 18 V Over Full …
